Verilog-Modelled Single Cycle Processor

This project involves using the Verilog modeling language to design a single-cycle ARMv8 ISA processor, by meticulously creating data path components for seamless instruction execution and efficient data handling.





About The Project

In an ambitious project aimed at understanding the intricacies of processor design, I undertook the task of modeling a single-cycle ARMv8 ISA processor using the hardware description language Verilog. The project's cornerstone was to meticulously construct each datapath component, ensuring that they function cohesively in a simulation of real-world processing tasks.


My approach was systematic: beginning with the instruction memory, which serves as the repository for the executable instructions, I then architected the data memory – a crucial component responsible for storing and retrieving data. The control unit was another pivotal design, determining the processor's operational sequence, while the Arithmetic Logic Units (ALUs) were engineered to perform fundamental arithmetic and logical operations essential for the processor's functioning.


Bringing these individual components to life involved a deep dive into the Verilog language, with a focus on crafting precise and efficient code that reflects the intended hardware behavior. After rigorous testing and validation of each module, I embarked on the challenging yet rewarding process of integrating them. This culminated in a final Verilog source file, representing a harmonious orchestra of instruction memory, data memory, control unit, and ALUs, all working in unison.


The outcome was a fully functional single-cycle ARMv8 ISA processor model, a testament to the robustness of my design approach and a practical demonstration of my proficiency in hardware description and digital design principles.